New Fault Isolation Method during Functional Test in Manufacturing

Abstract

Stop Clock Design-for-Testability (DFT) and Scan Dump DFT are integrated and implemented to trap the digital logic inside combinational and sequential logics for fault isolation (FI) purpose. Both DFTs enable functional test result to be dumped out structurally during functional test at manufacturing. Validation is performed on RTL simulation using test pattern and it is shown that the real silicon data matched the simulation results. Hence a new FI method has been established on the fly, capable in manufacturing.