New Failure Mechanism Induced by Current Limit for Superjunction MOSFET Under Single-Pulse UIS Stress

Abstract

New failure mechanism induced by current limits has been investigated for the superjunction MOSFET (SJ-MOSFET) under single-pulse unclamped inductive switching (UIS) test stress. It is found that the local charge imbalance ( Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> > Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ) at the chip corner produces a hotspot during the UIS test. The failure of the device induced by the hotspot depends on the magnitude of the avalanche current. For a low avalanche current, the avalanche current is redistributed from the local charge imbalance region to the charge balance region due to the lattice temperature increasing, resulting in the local heating toward the full-scale heating. However, for a high avalanche current, the negative differential resistance (NDR) effect plays a dominant role in the local charge imbalance region, decreasing the dynamic breakdown voltage (BV) sharply. Therefore, the hotspot is locked at the charge imbalance region; then, the device is destroyed in a short time. Finally, an SJ-MOSFET with more p-type charges at the chip corner is produced to improve the avalanche capability relating to the current limit, also verifying the mechanism analysis.