New encoding/decoding methods for designing fault-tolerant matrix operations

Abstract

The algorithm-based fault tolerance (ABFT) provides low-cost error protection for VLSI processor arrays used in real-time digital signal processing. Several ABFT techniques (weighted check-sum) have be proposed to design fault-tolerant LU decomposition, QR decomposition, and matrix inversion. In these schemes, encoding/decoding uses either multiplication or division so that overhead is high. In this paper, we propose new encoding/decoding methods for designing fault-tolerant matrix operations. Since the new encoding/decoding methods use only additions and subtractions, the overhead of a fault-tolerant processor array can be drastically reduced.