Evaluating reliability improvements of fault tolerant VLSI processor arrays

Abstract

An important and meaningful criterion for evaluating a VLSI processor array incorporating an ABFT (algorithm-based fault tolerance) technique is identified. A reliability model which can be used to accurately compute the reliability improvement of a fault-tolerant processor array is established. Examples showing that, when an ABFT technique is incorporated, the reliability improvement depends on the size of the processor array, the nature of the failure, and the failure rate are presented. Therefore, by using the reliability model and methods discussed here, a system designer will be able to determine whether it is beneficial to incorporate an ABFT technique a priori. Moreover, if the reliability of an ABFT processor array cannot meet the specified requirement, the proposed method can also be used as a guide to partition it into smaller ones so that this ABFT technique is still effective and a minimal amount of overhead is introduced. >