New developments in stacked die CSPs

Abstract

The market for stacked die and stacked packages is driven by portable applications that require extremely small form-factors. Stacked die packages continue to see double digit growth. Almost every mobile phone and digital camera contains at least one stacked die CSP. Stacked die packages are also found in personal digital assistants (PDAs). While much of the volume has been in the two die stacked package, an increasing number of stacked die packages with three, four, or five die are shipping. In addition, Fujitsu Microelectronics, ChipPAC, and Intel are offering eight die stacked CSPs - some with interposers between the die. The majority of packages shipping today are wire bonded, but flip chip is on the roadmaps of both semiconductor makers and IC package contract assembly houses. While most of the stacked die packages shipped historically are memory (flash and SRAM), packages containing logic devices are also increasingly moving into production. Among the advantages of stacked solutions include smaller form factor, fast turn-time, and low NRE costs (compared to a single die design). The key challenges of stacked die products include both logistical and engineering issues. Issues related to die include wafer thinning, bare die, known good die (KGD), die attach and wire bond, and thermal dissipation. One solution to the bare die or KGD problem is to stack packages that are tested. Some of these packages may contain more than one die. Several configurations from companies including Intel and Fujitsu are in production.