New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology

Abstract

A new design concept for on-chip electrostatic discharge (ESD) protection circuits with the already-on device is proposed to provide efficient ESD protection for ICs in nanoscale CMOS technologies. The already-on device used in this work is the native-NMOS-triggered SCR (NANSCR) device, which has a trigger voltage of almost zero in a 130-nm CMOS process. The already-on NANSCR has the lowest trigger voltage, smaller turn-on resistance, lower holding voltage, faster turn-on speed, and higher ESD level than those of traditional design.