An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology

A.Z.H. Wang,Chen-Hui Tsay Chen-Hui Tsay

doi:10.1109/4.896227

An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology

A.Z.H. Wang, Chen-Hui Tsay Chen-Hui Tsay

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https://doi.org/10.1109/4.896227

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Journal: IEEE Journal of Solid-State Circuits	Publication Date: Jan 1, 2001
Citations: 28

Affiliation: Illinois Institute of Technology

#On-chip Electrostatic Discharge Protection Circuit #Electrostatic Discharge Protection Circuit + Show 8 more

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Abstract

A novel low-trigger dual-direction on-chip electrostatic discharge (ESD) protection circuit is designed to protect integrated circuits (ICs) against ESD surges in two opposite directions. The compact ESD protection circuit features low triggering voltage (/spl sim/7.5 V), short response time (0.18-0.4 ns), symmetric deep-snap-back I-V characteristics, and low on-resistance (/spl sim//spl Omega/). It passed the 14-kV human body model (HBM) ESD test and is very area efficient (/spl sim/80 V//spl mu/m width). The new ESD protection design is particularly suitable for low-voltage or multiple-power-supply IC chips.

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