Abstract
Point-of-load DC-DC converters for current and next generation of ICs for communication systems and microprocessors are increasingly becoming stricter than ever. This is due to the required tight dynamic tolerances allowed for supply voltages and high dynamic performance demand coupled with very high power density. A new coupled-inductors current-doubler topology is proposed in this paper. The advantages of the proposed topology include higher voltage step-down ratio suitable for lower output voltages, better current ripple cancellation resulting in lower output current ripple, smaller isolation transformer turns ratio and lower secondary turns current when used in isolated topology, and can be designed to achieve symmetric transient response at both step-up and step-down transients when used in nonisolated topology. Theoretical analysis and simulation results are presented, and verified by experimental results.
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