Abstract
This paper presents a neural-network based nonlinear behavioral modelling of I/O buffer that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variations. Model structure and I/O device characterization along with extraction procedure were described. The last stage of the I/O buffer is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The mathematical model structure of the predriver was derived from the analysis of the large-signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure was considered in this work. Timing series data which reflects the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, were used to train the NN model. The proposed model was implemented in the time-domain solver and validated against the reference transistor level (TL) model and the state-of-the-art input-output buffer information specification (IBIS) behavioral model under different scenarios. The analysis of jitter was performed using the eye diagrams plotted at different metrics values.
Highlights
Signal and power integrity (SPI) simulation of high-speed mixed-signal I/O links is a fundamental task that designers perform and iterate until meeting the specification of timing and amplitude distortions
A behavioral model based on input-output buffer information specifications (IBIS) or other parametric and enhanced equivalent circuit approaches can be used in SPI simulation flow that balances the tradeoff between simulation time and computational resources with good accuracy [2,3]
This section describes the generation of behavioral model of I/O buffer both stages under distinct power and ground supply voltage (PGSV) variations
Summary
Signal and power integrity (SPI) simulation of high-speed mixed-signal I/O links is a fundamental task that designers perform and iterate until meeting the specification of timing and amplitude distortions. Distortions, which are the input of the last-stage driver model This shortcoming supply ripple voltage derived from frequency domainmodels simulations this shortcoming limits the usage of the behavioral when[8,9,10,11,12]. For ripple instance, PGSVderived variations at frequency the predriver and last stage would distort the timing supply voltage from domain simulations [8,9,10,11,12]. This work addressed the challenge of capturing the effect of PGSV noise applied on the stages of the driver (e.g., predriver and last stage) by investigating a neural-network (NN)-based parametric model for modelling the predriver’s timing and amplitude distorbased parametric model for modelling the predriver’s timing and amplitude distortions, tions, as it is powered independently from the last-stage one.
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