IBIS and Mpilog Modelling Frameworks for Signal Integrity Simulation

Abstract

This chapter outlines the structure of the modern integrated circuits (IC) and the necessity of the I/O buffers circuit for ensuring reliable chip-to-chip communication in high-speed digital communication I/O links. Nonlinear circuit simulation based on dc and transient analysis is discussed in order to properly figure out the importance of these algorithms by addressing their convergence issue and computational cost for signal integrity simulation. Moreover, the nonlinear dynamic intrinsic and extrinsic characteristics of the I/O buffers circuit are identified and analyzed. Moreover, this chapter describes IBIS and Mpilog modelling algorithms at circuit level and explains the reason behind the adoption of these modeling tools at different computer aided design (CAD) tools and design houses as opposed to the SPICE transistor level models in the simulation of printed circuit board (PCB) performance for signal and power integrity simulation. The different design steps of the system identification framework are detailed in the context of accurately capturing the nonlinear dynamic behavior of the I/O buffers electrical circuit. With the aim of analyzing the origins of behavioral modeling developed for output buffer/driver to capture its nonlinear and memory effects and in a way to establish a link with their modeling approaches through large-signal equivalent circuit model and parametric curve fitting techniques, a comprehensive overview of the mathematical modeling framework based on system identification theory is presented in this chapter. For sake of simplicity, the methodology is firstly described for one-port active devices. Then, it is extended to two-ports covering the black-box and the gray-box formulations and identification for modeling the driver’s nonlinear dynamic behaviors where the state-of the-art Input/output Buffer Information Specification (IBIS) and parametric modeling are analyzed and discussed.