Abstract
The move to many-core system is expected to become the dominant trend in the near future. With technology scaling into nanoscale regime, hundreds and even thousands of intellectual property (IP) cores can be integrated into a single chip. How to provide efficient and reliable communication between these IP cores becomes a bit problem. The conventional bus-based infrastructures are no longer sufficient to handle intensive on-chip communication. Network-on-chip (NoC) is emerging as an efficient solution to solve the aggravating scalability and bandwidth issues of on-chip communication by replacing traditional bus structures with a packet-switched network. This chapter is developed to introduce the common NoC architectures and the reliability issues facing in NoC design.
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