Negative Capacitance Junctionless Device With Mid-Gap Work Function for Low Power Applications

Abstract

This work demonstrates the systematic methodology to optimize the negative capacitance (NC) $n$ -type double gate (DG) junctionless (JL) device for low power (LP) and high-density (HD) applications. Results show that the positive charge density in the channel region of NCJL device induces negative internal gate voltage ( $V_{\text {int}}$ ) at zero gate bias ( $V_{\text {gs}} =0$ V), which helps to deplete the channel and significantly reduces the off-current ( $I_{\text {off}}$ ) compared to JL device. Conventional JL device requires a very high gate work function ( $\varphi _{\text {m}} \sim 5$ eV) to achieve volume depletion. However, NCJL device can lower $\varphi _{\text {m}}$ to mid-gap values while ensuring the full depletion in the channel and improving the on-current ( $I_{\text {on}}$ ). NCJL device with mid-gap $\varphi _{\text {m}}$ exhibits higher $I_{\text {on}}$ and lower $I_{\text {off}}$ compared to the performance target specified by International Roadmap for Devices and Systems (IRDS) for LP and HD applications.