Abstract
In this article, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectric on the I-V characteristics. Importantly, our model predicts that the negative capacitance minimizes short channel effects and enhances current overdrive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels. Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation.
Highlights
A dvanced aggressive scaling of conventional metal-oxidesemiconductor field-effect transistors (MOSFET) requires the use of advanced processing with multiple additive technology boosters, such as strain, high-k dielectrics with metal gate stacks, shallow junctions and the replacement of the silicon channel with materials having higher carrier mobility [1], [2]
In an attempt to remove all the limitations related to the junction engineering at nanoscale, the concept of junctionless field-effect transistors (JLFET) has been proposed, where the conduction in a very thin, highly doped semiconductor film is controlled by a gate field effect
We investigated by calibrated modeling and simulations, the effect of negative capacitance on the characteristics of junctionless transistors
Summary
A dvanced aggressive scaling of conventional metal-oxidesemiconductor field-effect transistors (MOSFET) requires the use of advanced processing with multiple additive technology boosters, such as strain, high-k dielectrics with metal gate stacks, shallow junctions and the replacement of the silicon channel with materials having higher carrier mobility [1], [2]. In order to take account the ferroelectric in junctionless transistors in a simple and compact model approach, in this work, we propose analytical and explicit relationships taking into account the negative capacitance effect in DoubleGate JLFET (NCDG JLFET) and evidences an amplification of the current-voltage dependence with respect to the ferroelectric thickness. This model relies on the charge-based approach developed in [27]–[33].
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