Negative-Bias Temperature Instability of p-GaN Gate GaN-on-Si Power Devices

Abstract

The threshold voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ th}}$ </tex-math></inline-formula>) of p-GaN GaN-on-Si power devices has been examined under negative-bias temperature instability (NBTI) stress conditions, and the physical mechanisms are evaluated using 2D device simulation and experimental data. Three regimes of <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ th}}$ </tex-math></inline-formula> shift (<inline-formula> <tex-math notation="LaTeX">$\Delta \text{V}_{\mathrm{ th}}$ </tex-math></inline-formula>) as a function of stress time and voltage magnitude at elevated temperatures have been investigated. Under the low gate stress condition, negative <inline-formula> <tex-math notation="LaTeX">$\Delta \text{V}_{\mathrm{ th}}$ </tex-math></inline-formula> follows the power-law characteristics resulting from the electron de-trapping/injection process from the p-GaN region to the channel. Under the mid-stress condition, a bidirectional <inline-formula> <tex-math notation="LaTeX">$\Delta \text{V}_{\mathrm{ th}}$ </tex-math></inline-formula> was recognized due to spill-over electrons into the p-GaN gate from the channel. At high gate stress, the hole accumulation at the interface between the Schottky contact and p-GaN is responsible for the negative <inline-formula> <tex-math notation="LaTeX">$\Delta \text{V}_{\mathrm{ th}}$ </tex-math></inline-formula>.