Abstract
AbstractElectromigration measurements of dual-damascene VLSI copper interconnect with sputtered TiN barrier was performed to measure both long-line (Jmax) performance and EM threshold (JLmax). Wafer-level stress of via chains with various segment lengths was combined with a statistical efficient experiment design to explore various conditions with minimum sample size. Resistance saturation was observed with exponential time constant corresponding to vacancy diffusivity. Time to opens failure by resistance increase follows Black's equation with current exponent n=1.90 and activation energy Ea=0.94 eV. Thermal gradients due to high current stress were characterized and accounted-for in acceleration models.
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