Near Threshold Capacitance Matching in a Negative Capacitance FET With 1 nm Effective Oxide Thickness Gate Stack

Abstract

We report Negative Capacitance nFETs with a ~ 1 nm effective oxide thickness (EOT) gate stack. Experimental measurements show a clear steepening of the slope of the ID-VG characteristic in the weak inversion regime, indicating that a capacitance matching takes place there. This leads to non-linear behavior of the current in the log scale, which is not observed in conventional devices. Such steepening in the weak inversion regime leads to a significant increase in the achievable current at a constant VDD. At LG = 50 nm, our transistors show a larger than 2X increase in the ON current.