Near term solutions for 3D packaging of high performance DRAM

Abstract

The revolution in performance driven electronic systems continues to challenge the IC packaging industry. To enable the new generations of processors to reach their performance potential and to achieve greater memory density and bandwidth, many manufacturers have developed a number of two-die package interface formats. Effective 3D stacking of memory die elements can offer many benefits; improved performance, increased component density and greater surface area utilization. The methodology selected for package assembly, however, must consider process complexity, the costs associated with each process, overall package assembly yield and end product reliability. To ensure that the memory functions are able to support the increased signal speed of the new generations of memory, package developers are relying more and more on die-stack assembly techniques and process refinement. This paper briefly reviews current two-die package assembly methodologies for the high performance, synchronous dynamic random-access memory (SDRAM) and introduces, in greater detail, an innovative two-die, face-down package assembly developed specifically for the next generation center bond memory products.