Near‐Bulk Conductivity of Gold Nanowires as Nanoscale Interconnects and the Role of Atomically Smooth Interface

Abstract

The electronics industry has consistently decreased the dimensions of structural components and they are now well into the nanoscale range. Naturally, a significant portion of the chip is composed of interconnects. Besides, the engineering problems associated with short wavelength lithography to achieve smaller components, the performance of increasing number of interconnections has become one of the biggest limiting factors in device performance. [1,2] The power loss, signal degradation, interconnection delays, and other performance limitations related to interconnects should be minimized. The importance of such a task can be seen from the perspective of power dissipation by computation elements. The energy dissipation density in electronic chips approaches that in nuclear reactors. [3,4] Therefore, the decrease of the resistivity of metal interconnects is one of the key challenges in the design of nanoscale electronic circuits. Intense studies on methods of preparation of interconnects by advanced lithographic techniques including e-beam lithography lead to the preparation of Au, Pd, Pt, and Cu nanowires (NWs) with resistivities much greater than the bulk metal value (see Supporting Information). [5‐11] The reason for the drastic increase in resistivity for NWs is that charge carriers experience grain boundaries reflections and surface scattering. The smaller the diameter of the conductor, the greater this effect becomes. Even NWs with diameters much above the nanometer scale can exhibit resistivities as high as two orders of magnitude greater that the bulk. [12]