NCFET: Opportunities & challenges for advanced technology nodes

Abstract

In ten years since the concept of negative capacitance (NC) was first postulated [1] there have been numerous experimental demonstrations of the effect [2, 3]. In addition, circuit simulations show that NCFET can provide one generation performance boost [4, 5]. But advanced technology nodes present new challenges for NCFET. In scaled fin pitch we have to find room for the interfacial layers (IL), ferroelectrics (FE), work function (WF) metal, and gate metal (Fig. 1). During FE layer formation process we need 10nm thick metal layer to enable uniform crystallization. That means that we have to either scale down the FE layer thickness or the WF metal. It seems that the scaling will necessitate thinner FE layer, which needs to be crystalized at higher temperature and it is much more prone to leakage. Resulting FE capacitance (C FE ) is too large in magnitude and hence there will barely be any NC effects (Fig. 2). To achieve steeper subthreshold slopes (SS), we have to use thicker FE and we are forced to reengineer the metal gate stack. Since the V TH of NCFET is determined by capacitance matching, it is more difficult to get a wide range for V TH (Fig. 3). The voltage gain in an NCFET depends on both gate and drain bias (V G and V D ) [4]. Because of the drain to gate coupling, the voltage at the internal gate node (V INT ) becomes less than the applied voltage at the external gate node (V G ) in the sub-threshold regime (Fig. 4(a)). In fact, for V GS TH , V INT becomes negative (Fig. 4(a)) [considering, no shift in V TH occurs through gate WF mismatch]. Therefore, despite having lower V TH , the I OFF in NCFET can be lower than the control device (Fig. 4 (b)) [4]. On the other hand, for V GS > V TH , V INT is enhanced beyond V G , as NC of the FE provides amplification. That accounts for the boost in I ON (Fig. 4 (b)).