Nanotopography produced by using a vacuum pin chuck and the flattening ability around its periphery

Abstract

In next-generation lithography, the problems of nanotopography and peripheral flatness deterioration caused by the flattening of a wafer with a current vacuum pin chuck must be solved. This paper describes the factors contributing to nanotopography and flatness deterioration, and determines the flattening ability around the periphery using a current pin chuck. It is shown that the nanotopography induced by clamping is very small after polishing of the chuck surface, but may increase above 10 nm due to pin wear. Since the ring seal used to prevent the leakage is 20–40 nm higher than the pins, the peripheral flatness of the wafer deteriorates. In addition, it is found that flattening a heavily warped wafer up to the wafer edge is difficult. As such, the current ring-seal-type chuck should be replaced with a static-pressure-seal-type chuck.