Abstract
This study proposes a logic non-volatile memory (NVM) device based on the state-of-the-art gate-all-around (GAA) nanosheet process. By adopting a complementary FET structure, we not only reduce the layout footprint area but also demonstrate the compatibility with sub-3nm nanosheet CMOS technology. We simulated the device in TCAD for program and erase operations, considering both Fowler Nordheim tunneling and hot carrier injection mechanisms. The memory window is optimized by adjusting the device structure, such as tunneling and blocking oxide thicknesses, top- and bottom-channel width, and the floating gate length, resulting in a significant enhancement in the memory window. Finally, NAND/NOR type CFET logic NVM are demonstrated to reveal the possible applications of gate-all-around stacked junctionless nanosheet transistor towards embedded flash.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
