Nanoscale Side-Contact Enabled Three Terminal Pr0.7Ca0.3MnO3 Resistive Random Access Memory for In-Memory Computing

Abstract

Resistive random-access memory (RRAM) devices that can execute logic are promising for in-memory computing. In state-of-the-art, a complementary resistive switch (CRS) bit-cell of two back-to-back bipolar RRAM shows a universal logic gate by multiple sequential write/compute operations using a resistance-based input/output (R-R logic) along with an extra read cycle. Here, we propose and experimentally demonstrate a three-terminal RRAM (3T-RRAM) to enable logic operations with voltage input and resistance output (V-R logic) in a single device and single write/compute cycle without a dedicated read cycle. Essentially, a nanoscale (~20nm) side-contact is added to a typical two-terminal Pt/Pr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ca <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> MnO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (PCMO)/W RRAM. As the PCMO RRAM is non-filamentary, all the terminals can act as in-out terminals. Hence, we utilize the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> terminal to read the state of the device while the other two terminals simultaneously performing the logic operation. Finally, we demonstrate the Implication (IMP) and converse IMP logic operations using 3T-RRAM. Such a device can enable area and energy-efficient in-memory computation.