Nanoscale device architecture to reduce leakage currents through quantum-mechanical simulation

Abstract

In this article, the effect of the gate tunneling current in ultrathin gate-oxide metal-oxide-semiconductor (MOS) devices of an effective gate length of 10nm is studied using a device simulation. A dramatic increase of gate and reverse-biased junction band-to-band-tunneling leakages in scaled devices results in a drastic increase in the total leakage power in a logic circuit. Here, we have proposed a device called parallel connected hetero material double-gate (PCHEM-DG) metal-oxide-semiconductor field-effect transistor (MOSFET) to facilitate the reduction of the effective gate leakage current over the conventional DG MOSFETs. First we have modeled the quantum transport phenomena in the device in order to gauge the potential effectiveness in nanoscale devices. In the study of the device, we have taken the ballistic electron transport in order to explore the effects of subband engineering on the MOS based technology. Then we have presented a simple model to evaluate the gate tunneling current in the device and compared and contrasted this current with the leakage current in the conventional DG MOSFET. We have compared the gate leakage current and the threshold voltage of the proposed device with MINIMOS 6.0 to prove the validity of our simulation results. It can be concluded that the scaling of the gate width cannot suppress the gate leakage, even if the specification of the threshold voltage is relaxed in order to shrink the gate width.