Nanoparticle-blockage-enabled rapid and reversible nanopore gating with tunable memory

The mobile devices such as smartphones and tablets are increasing processor speed and they are desired more energy. We focus on the emerging non volatile memory (NVM), which has gained attention in recent years. A non volatile memory is new memory technology such as SST-MRAM, PCM and ReRAM. Any devices also can be accessed in byte units, high speed nanoseconds access latency and higher write endurance than the flash memory. Thus, it is possible to replace the DRAM of the main memory by the NVM, it is possible to achieve reducing the power consumption. Although potentially possible of large capacity, NVM product of capacity greater than DRAM is currently not appeared now. We should provide a large memory space without performance degradation by in combination with NVM and other memory devices. In this paper, we propose a method to use the DRAM as swap space. The proposed method provides an experimental design of the non volatile main memory system. It enables both of high-performance and energy efficiency.

For database transaction processing, the authors compare the relative price-performance of storing data in volatile memory (V-mem), fault-tolerant non-volatile memory (FT-mem), and disk. First, they extend Gray's five-minute rule, which compares the relative cost of storing data in volatile memory as against disk for read-only data, to read-write data. Second, they show that because of additional write overhead, FT-mem has a higher advantage over V-mem than previously thought. Previous studies comparing volatile and non-volatile memories have focused on the response time advantages of putting log data in non-volatile memory. The authors show that there is a direct reduction in disk I/O, which leads to a much larger savings in cost using an FT-mem buffer. Third, the five-minute model is a simple model that assumes knowledge of inter-access times for data items. The authors present a more realistic model that assumes an LRU buffer management policy. They combine this with the recovery time constraint and study the resulting price-performance. It is shown that the use of an FT-mem buffer can lead to a significant benefit in terms of overall price-performance.

Rapid growth in technology is increasing day by day that demands computer systems to work better, should be reliable and have faster performance with fair cost and best functionalities. In the modern era of technology, memory files are used to shorten the performance gap between memory and storage. Sustainable in-memory file system (SIMFS) was the first that introduces the concept of open file address space into the address space of the process and exploits the memory mapping hardware while accessing files. The purpose of designing and implementing the SIMFS architecture is to achieve performance improvement of in-memory file system. SCMFS are designed for the storage class system that uses the presented memory management component in the operating system to assist in managing block, and it manages the space for each and every file adjacent to the virtual address space. A recent study has proposed that non-volatile memories are powerful enough to minimize the performance gap, as compared to previous generation non-volatile memories. This is because the performance gap between non-volatile and volatile memories has been reduced and there are possibilities of using a non-volatile memory as a computer’s main memory in near future. Lately, high-speed non-volatile storage media, such as Phase Change Memory (PCM) has come into view and it is expected that for storage device PCM will be used by replacing the hard disk in upcoming years. Moreover, the PCM is byte-addressable, it means that it can access individual byte of data rather than word and data access time is expected to be almost indistinguishable of DRAM, a volatile memory. These features and innovations in computer architecture are making the computer system more reliable and faster.

Tannic acid modified single nanopore with multivalent metal ions recognition and ultra-trace level detection

A single memory cell having both volatile memory (VM) and nonvolatile memory (NVM) functions with an independent asymmetric dual-gate structure is reported, as well as its programming methods. In the case of operating the device as a VM cell, a higher sensing margin is obtained, and an undesirable soft-programming issue is suppressed when a gate-induced drain leakage programming method is used. Additionally, the sensing margin and hold retention time of the VM operation are improved in a programmed state of the NVM function. These results indicate that the proposed device has potential for high-density embedded-memory applications.

Memories are made of this

Through the rapid development of latest hardware technology, high performance as well as miniaturized size is the essentials of embedded system to meet various requirements from the society. It raises possibilities of genuine realization of IoT environment whose size and battery must be considered. However, the limitation of battery persistency and capacity restricts the long battery life time for guaranteeing real-time system. To maximize battery life time, low power technology which lowers the power consumption should be highly required. Previous researches mostly highlighted improving one single type of memory to increase ones efficiency. In this paper, reversely, considering multiple memories to optimize whole memory system is the following step for the efficient low power embedded system. Regarding to that fact, this paper suggests the study of volatile memory, whose capacity is relatively smaller but much low-powered, and non-volatile memory, which do not consume any standby power to keep data, to maximize the efficiency of the system. By executing function in specific memories, non-volatile and volatile memory, the quantitative analysis of power consumption is progressed. In spite of the opportunity cost of all of theses extra works to locate function in volatile memory, higher efficiencies of both power and energy are clearly identified compared to operating single non-volatile memory.

This book explores the implications of non-volatile memory (NVM) for database management systems (DBMSs). The advent of NVM will fundamentally change the dichotomy between volatile memory and durable storage in DBMSs. These new NVM devices are almost as fast as volatile memory, but all writes to them are persistent even after power loss. Existing DBMSs are unable to take full advantage of this technology because their internal architectures are predicated on the assumption that memory is volatile. With NVM, many of the components of legacy DBMSs are unnecessary and will degrade the performance of data-intensive applications. We present the design and implementation of DBMS architectures that are explicitly tailored for NVM. The book focuses on three aspects of a DBMS: (1) logging and recovery, (2) storage and buffer management, and (3) indexing. First, we present a logging and recovery protocol that enables the DBMS to support near-instantaneous recovery. Second, we propose a storage engine architecture and buffer management policy that leverages the durability and byte-addressability properties of NVM to reduce data duplication and data migration. Third, the book presents the design of a range index tailored for NVM that is latch-free yet simple to implement. All together, the work described in this book illustrates that rethinking the fundamental algorithms and data structures employed in a DBMS for NVM improves performance and availability, reduces operational cost, and simplifies software development.

P.12.5 Subunit specific effects of the invariant AChR Cys-loop Aspartate residues on gating and AChR expression

Reducing power consumption is a serious issue for today's computer systems. The measure to that issue, nonvolatile memory (NVM) and heterogeneous multicore architecture (HMA) draw attention. Non-volatile memory is the device that can maintain data without continuous power supply. This nonvolatile memory enable to reduce power consumption of main memory and zero-overhead hibernation. Heterogeneous multi-core architectures combine different cores. The cores are different each other in terms of instruction set architecture, circuit size and so on. Combination of various characteristics has significant possibility to achieve energy-efficient computer system. For the above reasons, combination of NVM and HMA enable to reduce power consumption of today's computer systems. Assuming using non volatile main memory, Operating System (OS) must be strict about memory management. Because, running time of OS go longer and risk of memory leaks get higher. In addition, code quality of OS must be high. To keep code quality, strong typing is useful. However C, which is mainstream of OS implementation, do not have mechanism avoid memory leak and strong typing mechanism. To solve this issue, there are some researches of implementing OS in Java have many case. However, previous works have certain performance problem. To solve this, we propose a new operating system architecture. This architecture aims that native machine code run as user programs while OS kernel is implemented in java. In this paper, we describe proposed architecture, explain a preliminary implementation of it, and show experiment by that implementation.

Non-volatile Memory is promising to persistent data storage, which has outstanding advantages against traditional storage devices such as HDD and SSD. One of its hugest advantages is its DRAM-like read latency and micro second level write latency, which is several hundred times faster than the original block device. However, one of the issues on using non-volatile memory as storage device is designing a suitable indexing system for data stores there, in which the characteristics of non-volatile memory can be able to make full use of. The state of the art indexing systems of non-volatile key-value stores are usually based on B+-tree or its variant, which are originally designed for mechanic hard disk and volatile memory. The semantics of B+-tree requires inside data being sorted and frequent split and merge for keeping its balance. However, both of sorting and splitting will cause extra write to non-volatile memory, which will downgrade the performance. As a result, B+-tree and its variant may not be naturally suitable for non-volatile memory. In this paper, we proposed a skiplist based indexing system for non-volatile memory key-value store(NV-Skiplist), which can take fully use of the features of both the non-volatile memory and DRAM. NV-Skiplist constructs its bottom layer in the non-volatile memory for data persistence and supporting range scan, it also builds its upper layers in the DRAM to retain fast index searching and prevent large consistent overhead. We also introduced a multi-ranged variant to increase the search performance. We evaluate the performance of NV-Skiplist on a non-volatile memory emulator with a server that has Intel Xeon E5-2620 v2 processor. The experimental results show that our design outperforms the original tree-based non-volatile key-value store on both insertion and search performance by both 27% and 12% in each case.

Hydrophobicity is a fundamental property that is responsible for numerous physical and biophysical aspects of molecular interactions in water. Peculiar behavior is expected for water in the vicinity of hydrophobic structures, such as nanopores. Indeed, hydrophobic nanopores can be found in two distinct states, dry and wet, even though the latter is thermodynamically unstable. Transitions between these two states are kinetically hindered in long pores but can be much faster in shorter pores. As it is demonstrated for the first time in this paper, these transitions can be induced by applying a voltage across a membrane with a single hydrophobic nanopore. Such voltage-induced gating in single nanopores can be realized in a reversible manner through electrowetting of inner walls of the nanopores. The resulting I-V curves of such artificial hydrophobic nanopores mimic biological voltage-gated channels.

Magnetoelectric coupling lights up spintronics path: Lithium battery ideas to tune magnetism

In typical cryptographic applications, the secret keys are stored in volatile or nonvolatile memory (NVM). In the latter case, they remain in memory and can be retrieved even when the power is turned off. Even volatile memory is vulnerable to attacks if one has physical access to it. Thus the traditional approaches to key storage are not favored, especially in high-security applications.

Understanding the endocytic process of nanoparticles (NPs) with different mechanical rigidities is critical to develop effective drug delivery vectors. Here, we perform experiments, coarse-grained molecular dynamics simulations, and theoretical analyses to investigate the role of NPs' mechanical rigidity in the cellular endocytic process. Experiments based on two types of engineered Au NPs that have similar properties but different rigidities are performed in order to investigate their cellular uptake efficiencies, and it has been found that the more rigid NPs can achieve a higher cellular uptake efficiency. Simulation results confirm that rigid NPs can achieve full internalization by forming a complete double-layer endosome coating, while relatively soft NPs can only reach 40% surface coverage by membrane lipids. Simulation results capture an intriguing translocation of multiple NPs with different rigidities in a cooperative manner where the NPs' mechanical rigidities regulate their translocation efficiencies. We find that theoretically rigid NPs require less energy to overcome the energy barrier for membrane internalization than soft NPs do, which is in good agreement with experiment and simulation results. This synergetic study offers useful insight into the design principle of a general NP-based drug delivery vector as well as the promising biomedical application of NP-based medicine.