Nanometer-scale silicon mosfets

Abstract

Abstract New fabrication techniques based on e-beam lithography and plasma etching have been used to make silicon MOSFETs with minimum features as small as 40 nanometers for use in both fundamental physical measurements and for more conventional device applications. Long (1 micron) devices with narrow (down to 40 nm) channels have been used to study electron transport in 1-dimensional systems and search for quantum phenomena in small structures. As the width of the inversion layer is reduced, a large increase in the low frequency noise is observed. By adjusting the gate voltage and temperature, well defined discrete switching between two levels can be observed in the drain conductance. This behavior can be identified as changes in mobility caused by the trapping of individual electrons in states near the Si/SiO2 interface. Measurements of the frequency and duty cycle of the switching as functions of temperature and gate voltage yield information about trap energy and spatial location. This new spectroscopy may offer insight into the fundamental nature of noise in MOSFETs. For more standard applications, short gate (down to 70 nm) buried channel MOSFETs have been made using a new technique that maintains high output resistance while providing very low input capacitance. With proper channel doping, the usual parasitic drain resistance can be converted into a JFET in series with the short gate MOSFET. This intrinsic CAS code MOS FET (CASFET) is the first device to show long channel behavior with gate lenghts this short. The short gate reduces input capacitance and the cascode configuration leads to low Miller capacitance and high voltage gain. Simulations indicate that an intrinsic frequency above 30 GHz may be possible. This device may find application in analog and digital circuits requiring the lowest possible input and feedthrough capacitance.