Abstract
The aim of this paper is to present a flexible and open-source multi-scale simulation software which has been developed by the Device Modelling Group at the University of Glasgow to study the charge transport in contemporary ultra-scaled Nano-CMOS devices. The name of this new simulation environment is Nano-electronic Simulation Software (NESS). Overall NESS is designed to be flexible, easy to use and extendable. Its main two modules are the structure generator and the numerical solvers module. The structure generator creates the geometry of the devices, defines the materials in each region of the simulation domain and includes eventually sources of statistical variability. The charge transport models and corresponding equations are implemented within the numerical solvers module and solved self-consistently with Poisson equation. Currently, NESS contains a drift–diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) solvers. The NEGF solver is the most important transport solver in the current version of NESS. Therefore, this paper is primarily focused on the description of the NEGF methodology and theory. It also provides comparison with the rest of the transport solvers implemented in NESS. The NEGF module in NESS can solve transport problems in the ballistic limit or including electron–phonon scattering. It also contains the Flietner model to compute the band-to-band tunneling current in heterostructures with a direct band gap. Both the structure generator and solvers are linked in NESS to supporting modules such as effective mass extractor and materials database. Simulation results are outputted in text or vtk format in order to be easily visualized and analyzed using 2D and 3D plots. The ultimate goal is for NESS to become open-source, flexible and easy to use TCAD simulation environment which can be used by researchers in both academia and industry and will facilitate collaborative software development.
Highlights
Further down-scaling of Complementary Metal-Oxide Semiconductor (CMOS) circuits has become increasingly complex and the fundamental challenges that the semiconductor industry faces at the device level will deeply affect the design of the next-generation integrated circuits and systems [1, 2]
The methodology to generate the aforementioned sources of variability is described below: Random Discrete Dopants In order to introduce random discrete dopants in the structure, we have adopted a rejection technique which is based on the atomic arrangement in the crystal lattice of the corresponding material [10]
Line edge roughness Line Edge Roughness (LER) is generated at the interface between the channel material and the gate oxide using the same approach described in Ref. [11]
Summary
Further down-scaling of Complementary Metal-Oxide Semiconductor (CMOS) circuits has become increasingly complex and the fundamental challenges that the semiconductor industry faces at the device level will deeply affect the. It is important for such tools to be user-friendly and to be published as an open-source software to allow collaboration and co-development by both industry and academia all over the world. This will allow a collaborative effort of the electron device community to find the solutions for tomorrow CMOS circuit designs.
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