Abstract
The most important requirement for NAND flash memory is a low bit cost. This chapter discusses the NAND flash memory cell and its scaling technologies. Requirements for isolation in NAND flash memory cell are more severe than other devices due to high-voltage operation during programming. Therefore, it was difficult to scale down of local oxidation of silicon (LOCOS) isolation width beyond 1.5- ?>m width due to boron diffusion from isolation bottom by LOCOS oxidation process. Then, a new field through implantation (FTI) process was developed. Next, the self-aligned shallow trench isolation cell (SA-STI cell) with floating gate (FG) wing had been developed. The chapter presents the planar FG cell and also discusses the side wall transfer-transistor (SWATT) cell as alternate memory cell technology for a multilevel NAND flash memory cell. Finally, it presents other advanced NAND flash device technologies.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
