高感度固体撮像素子の実現に向けたＭＯＳＦＥＴの高耐圧化

Abstract

A high-sensitivity solid-state image sensor consisting of an avalanche multiplication film and a CMOS read-out circuit is currently under investigation. The image sensor requires a high-voltage MOSFET to prevent the destruction of the read-out circuit by the high voltage required to achieve high sensitivity with avalanche multiplication in a photoconductive film. The destruction mechanism was revealed and various necessary conditions for a high-voltage MOSFET applicable to a 2/3-inch format image sensor were clarified. The new device has an n- electric field reduction layer surrounding an n+ drain contact. The distance between the gate electrode end and the drain contact end was set to 3μm. The simulation results show that the breakdown voltage increases as the impurity dosage is decreased and the highest breakdown voltage is obtained under implantation energy of 400 keV. The destruction of the new device was mainly due to the breakdown of a pn junction caused by current through the drain to the substrate rather than due to punch-through in which the current through the drain to the source crosses over an npn structure. The on-state resistance of the MOSFET increased abruptly when the Si surface in the electric reduction layer was nearly intrinsic. The breakdown voltage reached 54 V which was about five times as high as that of a conventional device. The device has a simple structure and is fabricated by means of a slightly modified process.