Multithreshold Voltage Technology for Low Power Bus Architecture

Abstract

Multithreshold voltage technology for low swing voltage bus architecture is proposed. Three new different classes of driver/repeater/receiver circuits are introduced. In the driver circuits, high threshold MOSFET transistor have been inserted in order to decrease its output swing voltage. To re-pull up the low swing to full swing voltage, innovated low delay cross-coupled latch circuit receivers are proposed. The same architecture with new repeater circuits based on multithreshold voltage are introduced in order to drive internal long interconnection lines and decreasing the total delay time. For 2V supply voltage using 0.5_m process technology, SPICE measurements show up to 20% improvement in the delay time and up to 50% saving in the total power dissipation comparing with the conventional CMOS bus architecture.