Abstract
In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
