Multi-Swarm based NoC Configuration and Synthesis

Abstract

Network-on-Chip (NoC) is a popular interconnection structure suited to many-core System-on-Chip (SoC). Assuming a mesh-based NoC, we explore the assignment of cores to NoC nodes and produce a best NoC configuration having minimal communication traffic, power consumption, and chip area. We employ pre-synthesized NoC components data to estimate power and area consumption of the interconnection network. NoC configuration and mapping problem is NP-hard, and we propose a hybrid scheme of swarm optimization that combines Tabu-list, sub-swarms, and Discrete Particle Swarm Optimization (DPSO). The main goal is to configure and synthesize NoC such that the total NoC latency, power consumption, and chip area are minimal. DPSO is used as the main optimization scheme and modified it such that each swarm particle move is influenced by NoC traffic. The methodology is tested for some multimedia application core graphs. It is determined that on average our tool reduced NoC area by 30% on average and reduced total NoC power (static + worst case dynamic) by 27.5% as compared to unoptimized NoCs.