Hybrid multi-swarm optimization based NoC synthesis

Abstract

Network-on-Chip (NoC) has been proposed as an interconnection framework for connecting large number of cores for a System-on-Chip (SoC). Assuming a mesh-based NoC, we explore the assignment of cores to cross-points and produce a best NoC configuration with minimum average communication traffic, power consumption and chip area. We use pre-synthesized network components data to estimate power and chip area of the NoC. NoC configuration and mapping problem belongs to NP-hard complexity set, therefore we propose a hybrid scheme of swarm optimization that combines Tabu-search, force-directed swapping, sub-swarms, and Discrete Particle Swarm Optimization (DPSO). The main goal of the optimization is to configure the NoC such that the total NoC latency, power consumption, and area occupied are minimal. DPSO is used as the main optimization scheme and modified so that each particle move is also influenced by a force derived from the NoC traffic matrix. The methodology is tested for some multimedia application core graphs as well as large network of randomly generated cores. It is determined that on average our hybrid technique required less number of iterations and time to reach an optimal solution when compared with existing NoC synthesis algorithms.