Multistep Transitions From Microstrip and GCPW Lines to SIW in 5G 26 GHz Band

Abstract

Substrate integrated waveguides (SIW) are a topic of interest for many researchers, due to their power handling capabilities and compatibility with planar processing techniques. These advantages make this technology an attractive candidate for fifth generation of cellular networks applications (5G). Thus, transitions from more common planar technologies to SIW have been designed to obtain a good performance. Several techniques have been used in these transitions, from the use of via holes as probes to the inclusion of lumped elements. We propose the use of cascaded linear tapers as a multistep transition in order to obtain a better performance, optimizing the designs for the 5G n258 band. As result, several transition configurations are optimized, measured and compared to simulations. The design process is performed using an heuristic approach, by just increasing the number of iterations. The optimization of sixteen transition topologies (four different configurations, with four different numbers of steps), is carried out by electromagnetic simulation in CST Microwave Studio. A comparison between the response of the different designs, and the number of iterations used to obtain them, is also presented. Simulations with an in-house full-wave solver are performed to validate the transitions. All the transitions have been manufactured in a low-cost single-layer printed circuit board technology on Rogers 4003C. A microstrip-to-SIW 4-step configuration, tested as a back-to-back prototype, exhibits an insertion loss between 2.0 dB and 2.2 dB and a return loss better than 20 dB dB, from 24.25 GHz to 26.5 GHz, including the effect of the end-launch connectors. Another GCPW-to-SIW 3-step configuration, tested also as a back-to-back prototype, experimentally shows from 24 GHz to 26.5 GHz a minimum return loss of 13 dB, and an insertion loss between 2.6 dB and 2.9 dB. The overall performance of the sixteen configurations validates the usefulness of the proposed design process.