Multi-step binary-weighted capacitive digital-to-analog converter architecture

Abstract

We present a capacitive digital-to-analog converter (DAC) architecture combining properties of the binary-weighted and serial charge-redistribution DACs to yield high integration density and high accuracy. The architecture provides the flexibility to trade area with conversion speed based on a set of area-speed-linearity constraints. We validate the architecture using a 10-bit two-step DAC example, simulated in a standard 0.35 mum CMOS technology. The 10-bit DAC occupies 32 times less area than the conventional 10-bit binary-weighted DAC, has low INL, good matching, and high tolerance to parasitic capacitance.