Domino ADC: A novel analog-to-digital converter architecture

Abstract

A novel analog-to-digital converter (ADC) architecture, named domino architecture, is introduced. The proposed idea can be taken as the continuous-time counterpart of SAR ADCs, and at the same time it resembles a series version of flash ADCs being implemented with much less circuit complexity and chip area. The basic idea is then pipelined in order to speed up the conversion process, leading in a conversion rate comparable to flash ADCs. Based on the proposed idea, an 8-bit ADC was designed in a 0.18um CMOS technology. The converter dissipates 21mW at 300MS/s, 19mW of which is dissipated by the track-and-hold blocks.