Abstract
This letter describes fixed-point implementations of the Winograd and prime factor FFT algorithms in which multiplications are replaced by additions, subtractions and shifts. Methods are described for minimizing the number of additions and subtractions, while achieving a required level of accuracy. VLSI implementation of the resulting FFTs could achieve very high speed and/or power efficiency. The method can be used to provide any chosen accuracy; examples are presented for 12 to 20 bit accuracy.
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