Abstract
Today's real-time image-processing technology has become a requirement for cellular smartphones, car information systems, and surveillance cameras. An image processor integrated into SoC devices for these applications requires high power efficiency for long battery life and high-temperature operation. In addition, the image processor must minimize silicon area for lower cost and be scalable for processing performance. Our previous work on a matrix processor (MTX) [1] achieves both high power and high area efficiency. Demand for higher resolution, advanced frame rates, and increased algorithm complexity is requiring image processors to scale upwards in performance. Our next-generation MX-2 core is developed by expanding processing elements (PE) of the MTX from 2b grain to 4b grain, and by increasing the operating frequency. The MX-2 core achieves both high power efficiency of 310GOPS/W and high area efficiency of 36.1GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . In addition, a pipelined architecture with an increased of scalable PEs (from 256 to 2048) is used to improve the power and area efficiency.
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