Abstract
Complex rotators are used in many important signal processing applications, including Cooley-Tukey and split-radix FFT algorithms. This paper presents methods for designing multiplierless implementations of fixed-point rotators and FFTs, in which multiplications are replaced by additions, subtractions, and shifts. These methods minimise the adder-cost (the number of additions and subtractions), while achieving a specified level of accuracy. FFT designs based on multiplierless rotators are compared with designs based on the multiplierless implementation of DFT matrix multiplication. These techniques make possible VLSI implementations of rotators and FFTs which could achieve very high speed and/or power efficiency. The methods can be used to provide any chosen accuracy; examples are presented for 12 to 26 bit accuracy. On average, rotators are shown to be implementable using 10, 12, or 15 adders to achieve accuracies of 12, 16, or 20 bits, respectively.
Highlights
Complex rotators, which multiply input values by e jθ for some θ, are used in many important applications, including fast fourier transform (FFT) algorithms, where they are known as “twiddle factors” [1]
In the case of radix-4 units, common subexpression elimination (CSE) applied to the whole radix-4 unit required on average almost twice as many adders as the use of three type-(viii) rotators together with the 16 real adders required for a 4-point FFT
Results are presented for 8- and 16-point DFTs with either 8 or 16 bits after the binary point, using the CSE methods in [8, 9]. (Note that the results in [8, Table VIII] are only for part of the computation; Table 2 shows the total addercount using the method in [8].) It can be seen that the matrix CSE method in [9] gives lower adder-cost
Summary
Complex rotators, which multiply input values by e jθ for some θ, are used in many important applications, including fast fourier transform (FFT) algorithms, where they are known as “twiddle factors” [1]. Many current systems require embedded FFTs, including orthogonal frequencydivision multiplexing modems for digital broadcasting, wireless networking, and telecommunications, and many more potential applications are anticipated. Because the real and imaginary parts of e jθ are in general irrational, the computation of such rotations, and of the FFT, is inherently inexact [1], so the requirement is always to achieve sufficient accuracy for an intended application. To reduce power consumption and increase speed, fixed-point arithmetic is often used. With recent advances in VLSI technology, “multiplierless” algorithms provide the option of further lowering power consumption and IC area, or greatly increasing throughput
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
