Multiple-valued logic memory circuit

Abstract

A new voltage-mode CMOS multiple-valued logic (MVL) memory circuit has been realized in a standard 2 μm p-well polysilicon-gate CMOS technology. This circuit requantizes MVL voltages during a setup clock mode and latches the input value during the hold clock mode. Using a 5 V supply and logical voltage increments of 1 -67 V, a quaternary memory circuit with a worst-case total setup and hold time of about 7 ns, and a best single-level transition total setup and hold lime of about 1 ns has been realized.