Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction Under Output Constraint

Abstract

A synthesis methodology for multiple scan trees that considers output pin limitation, scan chain routing length, test application time, and test data compression rate simultaneously is proposed in this paper. Multiple scan trees, also known as a scan forest, greatly reduce test data volume and test application time in system-on-chip testing. However, previous research on scan tree synthesis rarely considered issues such as, routing length and output port limitation, and hence created scan trees with a large number of scan output ports and excessively long routing paths. The proposed algorithm provides a mechanism that effectively reduces test time and test data volume, and routing length under output port constraint. As a result, very few or no output compressors are required, which significantly reduces the hardware overhead.