Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization

Abstract

An interconnect-driven layout-aware multiple scan tree synthesis methodology is proposed in this paper. Multiple scan trees greatly reduce test data volume and test application time. However, previous researches on scan tree synthesis rarely considered routing length issues, and hence create scan trees with long routing paths. The proposed algorithm effectively considers both test compression rate and routing length and hence produces better results than all previous known methods in both regards. In this method, a density-driven dynamic clustering algorithm is applied to determine scan cells in each scan tree. A compatibility based clique partition algorithm is used to determine tree topology, and then a Voronoi diagram is used to establish physical connections. Compared with the previous results on scan tree synthesis, the proposed method achieves better compression rate with smaller routing overhead.