Multiple Node Upset-Tolerant Latch Design

Abstract

This paper proposes a general method for the design of multiple node upset (MNU)-tolerant latches. First, two double node upset (DNU)-tolerant latches and one triple node upset (TNU)-tolerant latch are introduced. These proposed latches are highly resilient to DNUs and TNUs in terms of their output nodes. Then, a generalized MNU-tolerant latch structure is introduced based on the construction features of these latches. Massive Hspice simulations using silicon-on-insulator (SOI) technology indicate that none of the proposed latches would output an unrecoverable error. Finally, we compare our latches to the designs in other reports. The DNU-tolerant latch, DNUTL-1, demonstrates considerable advantages in terms of the area, propagation delay, power, and the delay-power-area product. Moreover, the DNUTL-1 master–slave flip-flop has good performance in setup time, hold time, and latching window.