Multiple nanowire gate field effect transistors

Abstract

Novel metal oxide semiconductor field effect transistor (MOSFET) architectures aimed at sub 1 V operation with enhanced current driving capability are reported. In our design, the planar channel region in a conventional MOSFET is replaced by an array of isolated Si wires. Directional metal coverage of the two sidewalls and the top surface of each Si wire help achieve enhanced gate control. Sub 1 V operation is achieved by reducing cross-sectional wire diameters to /spl sim/0.05 /spl mu/m. Since the conventional optical lithography techniques lack patterning resolution at this scale, a mix and match approach with interferometric lithography was employed. Super-resolution capability of interferometric lithography was applied to pattern nanoscale Si wires, while optical lithography was used to pattern non-critical device levels. Drain current versus gate voltage measurements of planar and wire MOSFETs demonstrated the superiority of the multiple nanowire gate design. Increasing the number of 0.05 /spl mu/m diameter wires significantly increased current flow in the channel region without sacrificing the low-voltage operation. The mix and match approach for patterning critical level nanoscale features represents a low-cost complement to optical lithography.