Multiple-bit-rate clock recovery circuit: theory

Abstract

The multiple-bit-rate clock recovery circuit has been recently proposed as a part of the communications packet switch. All packets must be the same length and be preceded by the frequency header, which is a number of consecutive ones (return-to-zero mode). The header is compared with the internal clock, and the result is used to set output clock frequency. The clock rate is defined by a number of fluxons propagating in ring oscillator, which is a close circular Josephson transmission line. The theory gives a bit rate bandwidth as a function of internal clock frequency, header length and silence time (maximum number of consecutive zeros in the packet).