Abstract
This paper reports multi-level-cell (MLC) operation of ferroelectric FETs (FeFET) arranged in AND-connected memory arrays with a bit-error rate (BER) of 4% when writing a random data pattern. The FeFETs with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> have been embedded in GlobalFoundries 28 nm bulk high-k metal gate (HKMG) technology and are based on a metal-ferroelectric-isolator-semiconductor (MFIS) stack. Due to the direct field influence of the ferroelectric layer onto the Si-channel current percolation paths (CPPs) dominate the state transition behavior. This results in device-to-device variation and contributes to the asymmetry in programming and erasing progression. For array operation, write schemes and state-preserving inhibit schemes are evaluated to cope with the influence of the CPPs. Finally, this enables us to take advantage of the MLC capabilities of FeFETs on the array level, further enhancing the storage density of the 1T memory cells. Robust retention is proven for the MLC states at 85°C as well as reliable rewritability of the memory array with changing input patterns.
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