Abstract
A new thin film fine line conductor preparation technology, the ground layer oxidation (GLO) process, which permits the mass production of 20-µm wide Ti-Pd-Au conductor lines is discussed. A combination of these fine lines and thick film dielectrics in multilayer substrates (MLS's) makes high interconnectiou densities for VLSI chips on muitichip packages (MCP's) possible. First, the design, manufacturing process, and inherent limitations of the gold selective plating process (GSP) for fine line generation are presented. The main limitation of the GSP process, the overetching of the Ti and Pd, is discussed and illustrated by experimental data. Next, the requirements for advanced VLSI packaging with multichip multilayer substrates are discussed. To meet the VLSI packaging need for thin film fine lines with widths too small to be realized by the GSP process, the ground layer oxidation process was conceived. The GLO process sequence is presented and experimental results are discussed. Finally, reliability data obtained with fine line conductors generated by the GLO process are shown.
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