Multi-Domain Verification of Power, Clock and Reset Domains

Abstract

Multi-Domain Verification (MDV) is a comprehensive approach that specializes in verifying design logic that straddles heterogeneous domains. An integrated circuit design can be conceptually disintegrated into multiple types of partition for domain analysis. For example, a modern design typically has a power domain partition, a clock domain partition, and a reset domain partition. Historically, domain analysis is confined to verification of the same domain (homogeneous domain): for example, power domain verification and clock domain crossing verification are performed separately. As designs become highly sophisticated and domains are inter-dependence of each other, this practice is no longer sufficient. Interactions between different types of domains (heterogeneous domains) is exceptionally complex and critical to the success of the device. Hence, a new methodology is required to verify them effectively. Multi-domain verification uses power domain information from the Unified Power Format (UPF) specifications, clock domain information from the clock tree models and reset domain information from the reset tree models. It employs specialized domain analysis and methodologies to examine the complex interactions of logic that straddles domain boundaries—among both homogeneous domains and heterogeneous domains. Multi-domain verification is an efficient way to ensure that all inter-domain issues are explored and verified with complete confidence.