Multi-dimensional design layout analysis in ASIC manufacturing

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Today electrical design engineers are witnessing a growing volume of design restrictions that has to be taken into account while making new designs and handle exceptions during design closure. Most of these new restrictions come from the new manufacturing processes that are employed in the ASIC fabrication. In this paper we discuss the state of art techniques that are being used for printing advanced design nodes. We first look at the multi-dimensional layout analysis to identify weak points. Then we look at graphical representation of design layout to capture the immediate neighbor impact. Lastly we look at the model based layout simulation that captures the process of image rendering to wafer. This paper proposes multi-dimensional layout analysis to be used in conjunction with the stand alone methodologies of rule and model based layout analysis. A 28nm design layout was analyzed to first identify weak points by multidimensional and graphical layout analysis. Then the shortlisted layout structures were confirmed by post-OPC simulation. The use of the combined approach will make the layout verification more exhaustive and efficient, effectively reducing the total cycle time for design to yield.