Multicore RISC Processor Implementation by VHDL for Educational Purposes

Abstract

With trends computer manufacturers to build computers that have Multicore processors, it becomes necessary to study the hardware architecture of this processor and the way of manage data between Cores. All the previous researches were designing single cycle processors or pipeline processors by FPGA (Field Programmable Gate Array). This is a first research work on parallel processing to design and implement a Multicore processor by FPGA. In this work Multicore processor has two Cores and each Core consists of 5-stage pipeline MIPS (Microprocessor without Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) processor. Separated data cache and instruction cache were added to each Core. MESI (Modified, Exclusive, Shared and Invalid) protocol is used to manage cache coherence and memory coherence which support Write-back policy where replacement algorithm is not needed. Many programs are tested on this design and the correct results were obtained. The VHDL (Very high speed integrated circuit Hardware Description Language) of the complete Multicore processor is implemented by using (Xilinx ISE Design Suite 13.4) Software and configured on FPGA Spartan-3AN starter kit and results from the kit were obtained.