Multichannel Clock and Data Recovery: A Synchronous Approach

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This brief proposes a scalable multichannel clock and data recovery architecture that exploits the synchrony of multiple point-to-point serial links and uses a single voltage-controlled oscillator (VCO) to drive multiple phase detection loops. The proposed architecture can be naturally reduced <emphasis emphasistype="boldital">by design</emphasis> to an ensemble of weakly interacting delay-locked loops. As a result, the jitter peaking problem is asymptotically eliminated, which makes this architecture well suited for use in long-haul repeater chains. Moreover, it allows controlling VCO jitter transfer to the recovered clock without affecting data jitter transfer. The architecture is demonstrated both by a Verilog-A behavioral model along with a rigorous system and statistical analysis. </para>